This invention relates generally to techniques for packaging integrated-circuit (IC) chips and, more particularly, to techniques for packaging wafer size or very large scale IC chips.
Conventional integrated-circuit (IC) chip packaging techniques involve hermetically sealing IC chips in individual chip packages to protect the chips from the environment. The chip packages are generally fabricated from a ceramic material, such as alumina (Al.sub.2 O.sub.3) or beryllia (BeO), or from a metal, such as copper. However, ceramic materials have relatively low thermal conductivities when compared with metals and are generally unsuitable for packaging wafer size or very large scale IC chips. This is because these chips draw large amounts of current and generate considerable amounts of heat that must be dissipated through the chip package. The use of ceramic materials for packaging these chips would either cause the chips to operate at excessively high temperatures or severely limit the density of the circuit elements that could be formed on the chips.
In contrast, metals have relatively high thermal conductivities and are quite suitable for packaging large scale IC chips. Conventional metal chip packages, such as the chip package disclosed in U.S. Pat. No. 4,524,238 to Butt, have a metal base, to which an IC chip is bonded, and a metal cover. The chip is hermetically sealed in the metal package by a solder glass or ceramic material having a coefficient of thermal expansion (CTE) that closely matches that of the metal base and cover. The coefficients of thermal expansion are matched to prevent any cracking of the solder glass or ceramic material due to temperature variations that occur during operation of the chip. Several solder glass materials, which have coefficients of thermal expansion in the range of approximately 160 to 170.times.10.sup.-7 /.degree.C., are suggested in the Butt patent for use in a copper or copper alloy chip package. Copper has a coefficient of thermal expansion of approximately 165.times.10.sup.-7 /.degree.C., from 0 to 100.degree. C.
However, as IC chips become very large and approach the size of a semiconductor wafer, in the range of 5 to 6 inches, differences in the thermal linear expansion curves of the copper and solder glass materials over the full operating temperature range of the chip become extremely critical. A thermal linear expansion curve is to be compared with a coefficient of thermal expansion which is the slope of the expansion curve at a specified temperature, such as room temperature (25.degree. C.). Even very small differences in the thermal expansions of these materials at some temperatures can cause cracking of a large scale chip package, resulting in the chip being ruined. The solder glass materials listed in the Butt patent generally do not have thermal linear expansion curves that closely match the thermal expansion curve of copper over the full operating temperature range of the chip. Accordingly, there has been a need for an improved packaging material for use with wafer size or large scale IC chips. The present invention is directed toward this end.